Software Synthesis and Verification

Course code: ITI0130, ITI8530
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Previous courses: 2014

Time and place

Lectures: Wednesdays 14:00, ICT-A1
Labs: Wednesdays 16:00, ICT-401 - Evelin Halling (evelin.halling ätt ttu.ee)

Lecture notes

• Lecture 1: Introduction to formal methods
• Lecture 2: Modelling state transition systems
• Lecture 3: Temporal logic CTL*
• Lecture 4: CTL model checking
• Lecture 5: Timed automata and TCTL model checking
• Test 1: Model checking
• Lecture 7: Program specifications
• Lecture 8: Proof system of Hoare logic for while-programs

Labs

• Lab 1: Introduction to modelling in UPPAAL
  • UPPAAL website
  • Small tutorial on UPPAAL
  • Tutorial on UPPAAL
  • Slides: UPPAAL introduction
  • Model: Lamp example
  • Query: Lamp example
• Lab 2: Introduction to modelling in UPPAAL
  • Slides: Example and explanation
  • Model: Coffee machine
  • Query: Coffee machine
• Lab 3: Reader-Writer (unreliable) communication protocol
  • Slides: Example and explanation
• Lab 4: Leader election protocol
  • Slides: Explanation
  • The Leader Election Protocol (IEEE 1394)
  • Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394

Exercises

• Exercises 1: Model checking (explicit and symbolic state)

Resources

• Formal Methods Europe