Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel
Mine navigeerimisribale
Mine otsikasti
| 32. rida: | 32. rida: | ||
* [[Media:ITI8531_Lecture_5_18_TA_and_TCTL.pdf|Lecture 5]]: Timed automata and TCTL model checking | * [[Media:ITI8531_Lecture_5_18_TA_and_TCTL.pdf|Lecture 5]]: Timed automata and TCTL model checking | ||
* Practicing for Test 1 (see Exercises 1 below) | * Practicing for Test 1 (see Exercises 1 below) | ||
| + | ** [[Media:ITI8531_Exercises_1_2016.pdf|Exercises]]: Model checking | ||
* Test 1: Model checking ('''12.03.2019''') | * Test 1: Model checking ('''12.03.2019''') | ||
| − | |||
* [[Media:ITI8531_Lecture_6.1_18_Specifications.pdf|Lecture 7.1]]: Program specifications | * [[Media:ITI8531_Lecture_6.1_18_Specifications.pdf|Lecture 7.1]]: Program specifications | ||
* [[Media:ITI8531_Lecture_6.2_18_verification.pdf|Lecture 7.2]]: Proving partial correctness of programs | * [[Media:ITI8531_Lecture_6.2_18_verification.pdf|Lecture 7.2]]: Proving partial correctness of programs | ||
Redaktsioon: 3. märts 2019, kell 18:11
Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130
Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418
Lab assistant:
Evelin Halling
Contact: evelin.halling ätt ttu.ee,
Previous courses: 2014
Time and place
Lectures: Tuesdays 12:00, ICT-A1
Labs: Thursdays 10:00, ICT-A1 - Evelin Halling
New!
Exams:
- Thursday May 24, 10:00, room ICT-A1
- Thursday May 31, 10:00, room ICT-A1
Lecture plan
- Lecture 1: Introduction
- Lecture 2: Modelling state transition systems
- Lecture 3: Temporal logic CTL*
- Lecture 4: CTL model checking
- Lecture 5: Timed automata and TCTL model checking
- Practicing for Test 1 (see Exercises 1 below)
- Exercises: Model checking
- Test 1: Model checking (12.03.2019)
- Lecture 7.1: Program specifications
- Lecture 7.2: Proving partial correctness of programs
- Lecture 8: Proof techniques (1): derived rules, backwards proof, annotations
- Lecture 9: Proving total correctness of while-programs
- Lecture 14: Verifying nondeterministic and parallel programs
- Practicing for Test 2 (26.04.2018): Deductive verification of non-deterministic and parallel programs
- Genzen 1st order calculus: Genzen 1st order sequent calculus (proof rules)
- Test 2 (03.05.2018, 12.00): Deductive verification of sequential, non-deterministic and parallel programs
- Lecture 8: Program synthesis I
- Lecture 9: Program synthesis II
- Repetition of test 1 and test 2 (17.05.2018)
Labs
- Lab 1: Introduction to modelling in UPPAAL
- Slides: UPPAAL introduction
- Model: Light Controller Model
- Query: Light Controller Query
- For More reading, refer below links:
- Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL
- Slides: Model Checking introduction
- Model: ATM System Model
- Query: ATM System Query
- Lab 3: Understanding of Clocks and State Space Explosion in UPPAAL
- Slides: Uppaal Modelling Language
- Model: JobShop Model with three possible scenarios
- Query: JobShop Query
- Lab 4: Assignment I: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
- Lab 5: Assignment II: Leader election protocol
Exercises
- Exercises 1: Model checking (explicit and symbolic state)
- Exercises 2: Partial correctness of WHILE-programs
- Partial correctness of non-deterministic and parallel programs
- Exercises 3.1: Partial correctness of non-deterministic and parallel programs
- Exercises 3.2: Partial correctness of non-deterministic and parallel programs
- Exercises 3.3: Parallel programs with message passing
Resources
- Formal Methods Europe
- Genzen's proof system for 1st order logic:
- HL proof rules for sequential and parallel programs:
- Some guidlines how to find invariants
- Mike Gordon's lecture notes on Hoare logic [1]