Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

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Redaktsioon: 8. aprill 2015, kell 12:53

Course code: ITI0130, ITI8530
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418

Previous courses: 2014

Time and place

Lectures: Wednesdays 14:00, ICT-A1
Labs: Wednesdays 16:00, ICT-401 - Evelin Halling (evelin.halling ätt ttu.ee)

News 2015

Lecture notes

Lecture 1: Introduction to formal methods
Lecture 2: Modelling state transition systems
Lecture 3: Temporal logic CTL*
Lecture 4: CTL model checking
Lecture 5: Timed automata and TCTL model checking
Test 1: Model checking
Lecture 7: Program specifications
Lecture 8: Proving partial correctness of programs
Lecture 9.1: Proof techniques (1): derived rules, backwards proof, annotations
Lecture 9.2: Proof techniques (2): Array- and FOR-rule
Lecture 10: Proving total correctness of while-programs
Test 2: Deductive verification of sequential programs

Labs

Lab 1: Introduction to modelling in UPPAAL
- UPPAAL website
- Small tutorial on UPPAAL
- Tutorial on UPPAAL
- Slides: UPPAAL introduction
- Model: Lamp example
- Query: Lamp example
Lab 2: Introduction to modelling in UPPAAL
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
Lab 3: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
Lab 4: Leader election protocol
Lab 5: Design-by-Contract

Lab 7: Design-by-Contract
- Secure Database

Exercises

Exercises 1: Model checking (explicit and symbolic state)
Exercises 2: Partial correctness of WHILE-programs
- Example 1: Partial correctness of WHILE-loop
- Example 2: Partial correctness of FOR-loop

Resources

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