Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel

Allikas: Kursused
Mine navigeerimisribale Mine otsikasti
 
(ei näidata 6 kasutaja 142 vahepealset redaktsiooni)
4. rida: 4. rida:
 
'''Lecturer''': prof. Jüri Vain <br>
 
'''Lecturer''': prof. Jüri Vain <br>
 
'''Contact''': juri.vain ätt ttu.ee, ICT-418 <br>
 
'''Contact''': juri.vain ätt ttu.ee, ICT-418 <br>
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<!-- '''Lecturer''': Leonidas Tsiopoulos <br>
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'''Contact''': leonidas.tsiopoulos ätt ttu.ee, ICT-418 <br>
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'''Lecturer''': Maksym Bortin <br>
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'''Contact''': maksym.bortin ätt ttu.ee, room B404 in the Cybernetics Building <br>
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'''Lab assistant''':
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Evelin Halling <br>
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'''Contact''': evelin.halling ätt ttu.ee <br>
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-->
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Previous courses: [http://vana.cs.ttu.ee/tiki-index.php?page=ITI0060 2014]
 
Previous courses: [http://vana.cs.ttu.ee/tiki-index.php?page=ITI0060 2014]
11. rida: 23. rida:
 
==Time and place==
 
==Time and place==
  
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Lectures: Thursdays 12:00, ICT-A1 <br>
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Lectures: Thursdays 10:00, ICT-315 <br>
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Labs: Thursdays 10:00, ICT-405 - Evelin Halling (evelin.halling ätt ttu.ee)
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Labs: Thursdays 12:00, ICT-404 - Jüri Vain
  
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==News 2016==
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'''New!'''<br>
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* Written exam I: at 14.00 on May 27, Room ICT-411
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* Due to CORONA restrictions course is entirely running over Teams channel "Software synthesis and Verification"
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* Written exam II: at 14.00 on June 3, Room ICT-411
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'''Exams: (To Be Updated) '''
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<br>
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*  ... <br>
 +
** Exam is for those who have not passed any of the tests or want to improve their final mark
 +
<!--* ... '''
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 +
-->
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==Lecture plan - To be updated for Module II and III==
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* [[Media:ITI8531_Lecture_1_18_Intro.pdf|Lecture 1]]: Introduction
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* [[Media:ITI8531_Lecture_2_2022_transition_systems.pdf|Lecture 2]]: Modelling state transition systems
 +
* [[Media:ITI8531_Lecture_3_2022_CTL.pdf|Lecture 3]]: Temporal logic CTL*
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* [[Media:ITI8531_Lecture_4_18_modelchecking.pdf|Lecture 4]]: CTL model checking
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* [[Media:ITI8531_Lecture_5_22_symb_modelchecking.pdf|Lecture 5]]: Symbolic model checking
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* [[Media:ITI8531_Lecture_6_22_TA_and_TCTL.pdf|Lecture 6]]: Model checking TCTL
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* Practicing for Test 1: Model checking  [[Media:ITI8531_Exercises_1_2016.pdf|Exercises]]: (05.03.2019)
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* Test 1: Model checking ('''12.03.2019''')
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* [[Media:ITI8531_Lecture_6.1_18_Specifications.pdf|Lecture 6]]: Program specifications (19.03.2019)
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* [[Media:ITI8531_Lecture_6.2_18_verification.pdf|Lecture 7]]: Proving partial correctness of programs (19.03.2019)
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* [[Media:ITI8531_Lecture_7_18_proving (2).pdf|Lecture 8]]: Proof techniques (1): derived rules, backwards proof, annotations (26.03.2019)
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* [[Media:ITI8531_Lecture_8_18_total_correctness.pdf|Lecture 9]]: Proving total correctness of while-programs (26.03.2019)
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* [[Media:ITI8531_Lecture_9_2017_parallel_programs.pdf|Lecture 10]]: Verifying nondeterministic and parallel programs  (02.04.2019)
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* Practicing for Test 2: Deductive verification of non-deterministic and parallel programs (04.04.2019 at lab time)
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** [[Media:ITI8531_Genzen_1st_order_calculus.pdf|Genzen 1st order calculus]]: Genzen 1st order sequent calculus (proof rules)
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* Test 2: Deductive verification of sequential, non-deterministic and parallel programs ('''09.04.2019,at 12.00''')
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* [[Media:Software Synthesis - Overview of Temporal Synthesis - Lecture 11.pdf|Lecture 11]]: Software synthesis I (16.04.2019)
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* [[Media:Software Synthesis - Introduction to Acacia - Lecture 12.pdf|Lecture 12]]: Software synthesis II (23.04.2019)
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* [[Media:Software Synthesis - LTL Synthesis and Acacia II - Lecture 13.pdf|Lecture 13]]: Software synthesis III (30.04.2019)
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* [[Media:Software Synthesis - LTL Synthesis with Acacia part III - Lecture 14.pdf|Lecture 14]]: Software synthesis IV (7.05.2019)
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* [[Media:Software Synthesis - Lecture V - Recap.pdf|Lecture 15]]: Software synthesis (recap) and practicing for test  (14.05.2019)
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* Test 3: Software synthesis ('''16.05.2019''')
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* Retake of Test 2, 2nd task: ('''21.05.2019 at 12.00 (New!)''')
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** [[Media:Test_2_2019_lahendus.pdf|Eample_Solution]]: ('''Example solution of Task2 (NEW!)''')
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==Labs - To be updated from lab 4 onwards==
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* Exercise Environment for Module II:
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** Download and install the environment: [[Media:HoareLogic.tar| Hoare Logic environment]]
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* Lab 1: Introduction to modelling in UPPAAL
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** Slides: [[Media:UPPAAL Tutorial.pdf|UPPAAL introduction]]
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** Model: [[Media:LightController.xml|Light Controller Model]]
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** Query: [[Media:LightControllerQuery.q|Light Controller Query]]
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** For More reading, refer below links:
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*** [http://www.uppaal.org/ UPPAAL website]
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*** [http://www.it.uu.se/research/group/darts/uppaal/small_tutorial.pdf Small tutorial on UPPAAL]
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*** [http://www.it.uu.se/research/group/darts/papers/texts/new-tutorial.pdf Tutorial on UPPAAL]
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* Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL
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** Slides: [[Media:New_Lab2_MODEL_CHECKING.pdf|Model Checking introduction]]
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** Model: [[Media:Atm_system.xml|ATM System Model]]
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** Query: [[Media:Atm_system_query.q|ATM System Query]]
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* Lab 3: Understanding of Clocks and State Space Explosion in UPPAAL
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** Slides: [[Media:Lab3_Lab_Lecture.pdf|Uppaal Modelling Language]]
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** Model: [[Media:Jobber.xml|JobShop Model with three possible scenarios]]
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** Query: [[Media:Jobber_Query1.q|JobShop Query]]
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* Lab 4: Assignment I: Reader-Writer (unreliable) communication protocol
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** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
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* Lab 5: Assignment II: Leader election protocol
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** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
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** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
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** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
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** Reference solution: [[Media:FASDS.pdf|Chapter 12, page 172]]
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* Lab 13:
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** [http://web.iitd.ac.in/~sumeet/slide3.pdf LTL]
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* Lab 14:
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** [[Media:ITI8531_LTL_exercises.pdf|Exercises]]
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** [http://goal.im.ntu.edu.tw/wiki/doku.php GOAL tool]
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** [http://www.lsv.fr/~gastin/ltl2ba/ LTL2BA]
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* Lab 15
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** [[Media:ITI8531_LTL_assignments.pdf|LTL Assignment]]
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** [[Media:Software Synthesis and Verification LTL Assignment-Updated Spec.pdf|Updated Spec for LTL Synthesis Assignment]]
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** [[Media:Guidelines for Lab Exercise Report for Synthesis with Acacia.pdf|Guidelines for Assignment]]
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** [[Media:Acacia Installation Commands.pdf|Acacia Tool Installation Commands]]
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** [[Media:Acacia_Manual.pdf|Acacia Tool Installation Guidelines and Manual for Command Line Options]]
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<!--
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* Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL
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** Slides: [[Media:Lecture_5.pdf|The Mutual Exclusion Problem and Algorithms]]
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** Model: [[Media:Attempt1_Model.xml|First Attempt Algorithm Model]]
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** Query: [[Media:Attempt1_query.q|First Attempt Query]]
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* Lab 6: Lab Assignment: ATM System, JobShop, Implementation of Mutual Exclusion Algo.
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** Slides: [[Media:Lab_Assignments.pdf|Tasks and explanation]]
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* Lab 7-8: Assignment: Reader-Writer (unreliable) communication protocol
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** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
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* Lab 9: Assignment: Elevator Control
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** Slides: [[Media:ElevatorControl_V1_29062017.pdf|Example and explanation]]
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** Slides: [[Media:ModellingRequirement.pptx|Modelling Requirements]]
  
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==Lecture plan==
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* Lab 10: Final Assessment on 17 May 2018
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* [[Media:ITI8531_Lecture_1_16_intro.pdf|Lecture 1]]: Introduction
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** Lab defending of all given assignment.
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* [[Media:ITI8531_Lecture_2_16.pdf|Lecture 2]]: Modelling state transition systems
+
-->
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* [[Media:ITI8531_Lecture_3_16.pdf|Lecture 3]]: Temporal logic CTL*
 
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* [[Media:ITI8531_lecture_4_16.pdf|Lecture 4]]: CTL model checking
 
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* [[Media:ITI8531_Lecture_5_16_TA_and_TCTL.pdf|Lecture 5]]: Timed automata and TCTL model checking
 
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* Test 1: Model checking
 
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** [[Media:ITI8531_Exercises_1_2016.pdf|Exercises]]: Model checking
 
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* [[Media:ITI8531_Lecture_5_16_Specifications.pdf|Lecture 7]]: Program specifications
 
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* [[Media:ITI8531_Lecture_6_16_rules.pdf|Lecture 8]]: Proving partial correctness of programs
 
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* [[Media:ITI0130_lecture9_1_2015.pdf|Lecture 9.1]]: Proof techniques (1): derived rules, backwards proof, annotations
 
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* [[Media:ITI0130_lecture9_2_2015.pdf|Lecture 9.2]]: Proof techniques (2): Array- and FOR-rule
 
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* [[Media:ITI0130_lecture10_2015.pdf|Lecture 10]]: Proving total correctness of while-programs
 
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* Test 2 (05.05.2016): Deductive verification of sequential programs
 
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* [[Media:ITI0130_lecture11_2015nondeterministic.pdf|Lecture 11]]: Non-deterministic programs
 
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* [[Media:ITI0130_lecture_12_2015.pdf|Lecture 12]]: Parallel programs with shared variables
 
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* [[Media:ITI0130_lecture_13_2015.pdf|Lecture 13]]: Parallel programs with message passing
 
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* [[Media:ITI8531_lecture_14_2016.pdf|Lecture 14]]: Program synthesis
 
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* Test 3 (26.05.2016): Deductive verification of non-deterministic and parallel programs
 
  
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==Labs==
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<!--
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* Lab 1 -2: Introduction to modelling in UPPAAL
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* Lab 4: Assignment 1: Coffee Machine
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** [http://www.uppaal.org/ UPPAAL website]
 
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** [http://www.it.uu.se/research/group/darts/uppaal/small_tutorial.pdf Small tutorial on UPPAAL]
 
−
** [http://www.it.uu.se/research/group/darts/papers/texts/new-tutorial.pdf Tutorial on UPPAAL]
 
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** Slides: [[Media:ITI0130_uppaal_eng_2013.pdf|UPPAAL introduction]]
 
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** Model: [[Media:ITI0130_Light.xml|Lamp example]]
 
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** Query: [[Media:ITI0130_Light.q|Lamp example]]
 
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* Lab 3: Introduction to modelling in UPPAAL
 
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** Assignment: Coffee Machine
 
 
** Slides: [[Media:ITI0130_Lab1_Coffee_machine_2015.pdf|Example and explanation]]
 
** Slides: [[Media:ITI0130_Lab1_Coffee_machine_2015.pdf|Example and explanation]]
 
** Model: [[Media:ITI0130_Coffee.xml|Coffee machine]]
 
** Model: [[Media:ITI0130_Coffee.xml|Coffee machine]]
 
** Query: [[Media:ITI0130_Coffee.q|Coffee machine]]
 
** Query: [[Media:ITI0130_Coffee.q|Coffee machine]]
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* Lab 4: UPPAAL
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−
** Assignment: Reader-Writer (unreliable) communication protocol
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* Lab 6: Assignment 3: Leader election protocol  
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** Slides: [[Media:ITI0130_Lab2_2015.pdf|Example and explanation]]
 
−
* Lab 5: UPPAAL
 
−
** Assignment: Leader election protocol  
 
 
** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
 
** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]]
 
** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
 
** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)]
 
** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
 
** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394]
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* Lab 6: UPPAAL
+
** Reference solution: [[Media:FASDS.pdf|Chapter 12]]
 +
* Lab 7: Lab Exam
 
** Homework defenses
 
** Homework defenses
 +
 +
 
* Lab 7: KeY Introduction
 
* Lab 7: KeY Introduction
 
** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]]
 
** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]]
67. rida: 145. rida:
 
** Bank JML: [[Media:ITI0130_Lab7_2016_Bank_JML.zip|Bank JML]]
 
** Bank JML: [[Media:ITI0130_Lab7_2016_Bank_JML.zip|Bank JML]]
  
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<!--
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* Lab 5: Design-by-Contract
 
* Lab 5: Design-by-Contract
 
** [https://github.com/nhatminhle/cofoja Contracts for Java (Cofoja)]
 
** [https://github.com/nhatminhle/cofoja Contracts for Java (Cofoja)]
102. rida: 180. rida:
  
 
== Exercises==
 
== Exercises==
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* [[Media:Exercises1.pdf|Exercises 1]]: Model checking (explicit and symbolic state)
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* [[Media:Test 1_2017for practicing.pdf|Exercises 1]]: Model checking (explicit and symbolic state)
 
* [[Media:Exercises_2.pdf|Exercises 2]]: Partial correctness of WHILE-programs
 
* [[Media:Exercises_2.pdf|Exercises 2]]: Partial correctness of WHILE-programs
 
** [[Media:while_program_example_2015.pdf|Example 1]]: Partial correctness of WHILE-loop
 
** [[Media:while_program_example_2015.pdf|Example 1]]: Partial correctness of WHILE-loop
 
** [[Media:DEDUCTIVE_VERIFICATION_Example_2.pdf|Example 2]]: Partial correctness of FOR-loop
 
** [[Media:DEDUCTIVE_VERIFICATION_Example_2.pdf|Example 2]]: Partial correctness of FOR-loop
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* [[Media:Exercises__3.pdf|Exercises 3]]: Partial correctness of non-deterministic and parallel programs
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* Partial correctness of non-deterministic and parallel programs
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** [[Media:Exercises__3.pdf|Exercises 3.1]]: Partial correctness of non-deterministic and parallel programs
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** [[Media:Test3_exercises_solutions.pdf|Exercises 3.2]]: Partial correctness of non-deterministic and parallel programs
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** [[Media:Harjutused_3.pdf|Exercises 3.3]]: Parallel programs with message passing
  
 
==Resources==
 
==Resources==

Viimane redaktsioon: 9. veebruar 2023, kell 09:58

Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130

Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418


Previous courses: 2014


Time and place

Lectures: Thursdays 10:00, ICT-315
Labs: Thursdays 12:00, ICT-404 - Jüri Vain

New!

  • Due to CORONA restrictions course is entirely running over Teams channel "Software synthesis and Verification"

Exams: (To Be Updated)

  • ...
    • Exam is for those who have not passed any of the tests or want to improve their final mark

Lecture plan - To be updated for Module II and III

  • Lecture 1: Introduction
  • Lecture 2: Modelling state transition systems
  • Lecture 3: Temporal logic CTL*
  • Lecture 4: CTL model checking
  • Lecture 5: Symbolic model checking
  • Lecture 6: Model checking TCTL
  • Practicing for Test 1: Model checking Exercises: (05.03.2019)
  • Test 1: Model checking (12.03.2019)
  • Lecture 6: Program specifications (19.03.2019)
  • Lecture 7: Proving partial correctness of programs (19.03.2019)
  • Lecture 8: Proof techniques (1): derived rules, backwards proof, annotations (26.03.2019)
  • Lecture 9: Proving total correctness of while-programs (26.03.2019)
  • Lecture 10: Verifying nondeterministic and parallel programs (02.04.2019)
  • Practicing for Test 2: Deductive verification of non-deterministic and parallel programs (04.04.2019 at lab time)
  • Test 2: Deductive verification of sequential, non-deterministic and parallel programs (09.04.2019,at 12.00)
  • Lecture 11: Software synthesis I (16.04.2019)
  • Lecture 12: Software synthesis II (23.04.2019)
  • Lecture 13: Software synthesis III (30.04.2019)
  • Lecture 14: Software synthesis IV (7.05.2019)
  • Lecture 15: Software synthesis (recap) and practicing for test (14.05.2019)
  • Test 3: Software synthesis (16.05.2019)
  • Retake of Test 2, 2nd task: (21.05.2019 at 12.00 (New!))

Labs - To be updated from lab 4 onwards


Exercises

  • Exercises 1: Model checking (explicit and symbolic state)
  • Exercises 2: Partial correctness of WHILE-programs
  • Partial correctness of non-deterministic and parallel programs
    • Exercises 3.1: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.2: Partial correctness of non-deterministic and parallel programs
    • Exercises 3.3: Parallel programs with message passing

Resources

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