Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel
Mine navigeerimisribale
Mine otsikasti
(→Labs) |
(→Labs) |
||
| 54. rida: | 54. rida: | ||
*** [http://www.it.uu.se/research/group/darts/uppaal/small_tutorial.pdf Small tutorial on UPPAAL] | *** [http://www.it.uu.se/research/group/darts/uppaal/small_tutorial.pdf Small tutorial on UPPAAL] | ||
*** [http://www.it.uu.se/research/group/darts/papers/texts/new-tutorial.pdf Tutorial on UPPAAL] | *** [http://www.it.uu.se/research/group/darts/papers/texts/new-tutorial.pdf Tutorial on UPPAAL] | ||
| + | |||
| + | * Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL | ||
| + | ** Slides: [[Media:Lab2_MODEL_CHECKING.pdf|Model Checking introduction]] | ||
| + | ** Model: [[Media:Atm_system.xml|ATM System Model]] | ||
| + | ** Query: [[Media:Atm_system_query.q|ATM System Query]] | ||
* Lab 3: Introduction to modelling in UPPAAL | * Lab 3: Introduction to modelling in UPPAAL | ||
Redaktsioon: 22. veebruar 2018, kell 06:58
Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130
Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418
Lab assistant:
Deepak Pal
Contact: deepak.pal ätt ttu.ee,
Previous courses: 2014
Time and place
Lectures: Thursdays 10:00, ICT-A1
Labs: Thursdays 12:00, ICT-122 - Deepak Pal
New!
Exams:
- Thursday May 1, 10:00, room ICT-A2
- Thursday May 8, 10:00, room ICT-A2
Lecture plan
- Lecture 1: Introduction
- Lecture 2: Modelling state transition systems
- Lecture 3: Temporal logic CTL*
- Lecture 4: CTL model checking
- Lecture 5: Timed automata and TCTL model checking
- Practicing for Test 1 (see Exercises 1 below)
- Test 1: Model checking (16.03.2017)
- Exercises: Model checking
- Lecture 7: Program specifications
- Lecture 8: Program synthesis I
- Lecture 9: Program synthesis II
- Test 2 (13.04.2017): Program synthesis
- Lecture 11: Proving partial correctness of programs
- Lecture 12.1: Proof techniques (1): derived rules, backwards proof, annotations
- Lecture 12.2: Proof techniques (2): Array- and FOR-rule
- Lecture 13: Proving total correctness of while-programs
- Lecture 14: Verifying nondeterministic and parallel programs
- Test 3 (25.05.2017): Deductive verification of non-deterministic and parallel programs
Labs
- Lab 1: Introduction to modelling in UPPAAL
- Slides: UPPAAL introduction
- Model: Light Controller Model
- Query: Light Controller Query
- For More reading, refer below links:
- Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL
- Slides: Model Checking introduction
- Model: ATM System Model
- Query: ATM System Query
- Lab 3: Introduction to modelling in UPPAAL
- Assignment: Coffee Machine
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
- Lab 4: UPPAAL
- Assignment: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
- Lab 5: UPPAAL
- Assignment: Leader election protocol
- Slides: Explanation
- The Leader Election Protocol (IEEE 1394)
- Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394
- Reference solution: Chapter 12
- Lab 6: UPPAAL
- Homework defenses
Exercises
- Exercises 1: Model checking (explicit and symbolic state)
- Exercises 2: Partial correctness of WHILE-programs
- Partial correctness of non-deterministic and parallel programs
- Exercises 3.1: Partial correctness of non-deterministic and parallel programs
- Exercises 3.2: Partial correctness of non-deterministic and parallel programs
- Exercises 3.3: Parallel programs with message passing
Resources
- Formal Methods Europe
- Genzen's proof system for 1st order logic:
- HL proof rules for sequential and parallel programs:
- Some guidlines how to find invariants
- Mike Gordon's lecture notes on Hoare logic [1]