Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel
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** Slides: [[Media:Lab_Assignments.pdf|Tasks and explanation]] | ** Slides: [[Media:Lab_Assignments.pdf|Tasks and explanation]] | ||
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* Lab 4: Assignment 1: Coffee Machine | * Lab 4: Assignment 1: Coffee Machine | ||
** Slides: [[Media:ITI0130_Lab1_Coffee_machine_2015.pdf|Example and explanation]] | ** Slides: [[Media:ITI0130_Lab1_Coffee_machine_2015.pdf|Example and explanation]] | ||
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** Homework defenses | ** Homework defenses | ||
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* Lab 7: KeY Introduction | * Lab 7: KeY Introduction | ||
** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]] | ** Installation: [[Media:ITI0130_Lab7_2016_KeY.pdf|KeY Installation]] | ||
Redaktsioon: 29. märts 2018, kell 06:23
Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130
Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418
Lab assistant:
Deepak Pal
Contact: deepak.pal ätt ttu.ee,
Previous courses: 2014
Time and place
Lectures: Thursdays 10:00, ICT-A1
Labs: Thursdays 12:00, ICT-122 - Deepak Pal
New!
Exams:
- Thursday May 1, 10:00, room ICT-A2
- Thursday May 8, 10:00, room ICT-A2
Lecture plan
- Lecture 1: Introduction
- Lecture 2: Modelling state transition systems
- Lecture 3: Temporal logic CTL*
- Lecture 4: CTL model checking
- Lecture 5: Timed automata and TCTL model checking
- Practicing for Test 1 (see Exercises 1 below)
- Test 1: Model checking (16.03.2017)
- Exercises: Model checking
- Lecture 7: Program specifications
- Lecture 8: Program synthesis I
- Lecture 9: Program synthesis II
- Test 2 (13.04.2017): Program synthesis
- Lecture 11: Proving partial correctness of programs
- Lecture 12.1: Proof techniques (1): derived rules, backwards proof, annotations
- Lecture 12.2: Proof techniques (2): Array- and FOR-rule
- Lecture 13: Proving total correctness of while-programs
- Lecture 14: Verifying nondeterministic and parallel programs
- Test 3 (25.05.2017): Deductive verification of non-deterministic and parallel programs
Labs
- Lab 1: Introduction to modelling in UPPAAL
- Slides: UPPAAL introduction
- Model: Light Controller Model
- Query: Light Controller Query
- For More reading, refer below links:
- Lab 2: Validation (simulation) and verification (automatic model-checking) in UPPAAL
- Slides: Model Checking introduction
- Model: ATM System Model
- Query: ATM System Query
- Lab 3: Understanding of Clocks and State Space Explosion in UPPAAL
- Slides: Uppaal Modelling Language
- Model: JobShop Model with three possible scenarios
- Query: JobShop Query
- Lab 4-5: Implementation of Mutual Exclusion Algorithms in UPPAAL
- Slides: The Mutual Exclusion Problem and Algorithms
- Model: First Attempt Algorithm Model
- Query: First Attempt Query
- Lab Assignment: ATM System, JobShop, Implementation of Mutual Exclusion Algo.
- Slides: Tasks and explanation
- Lab 4: Assignment 1: Coffee Machine
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
- Lab 5: Assignment 2: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
- Lab 6: Assignment 3: Leader election protocol
- Lab 7: Lab Exam
- Homework defenses
Exercises
- Exercises 1: Model checking (explicit and symbolic state)
- Exercises 2: Partial correctness of WHILE-programs
- Partial correctness of non-deterministic and parallel programs
- Exercises 3.1: Partial correctness of non-deterministic and parallel programs
- Exercises 3.2: Partial correctness of non-deterministic and parallel programs
- Exercises 3.3: Parallel programs with message passing
Resources
- Formal Methods Europe
- Genzen's proof system for 1st order logic:
- HL proof rules for sequential and parallel programs:
- Some guidlines how to find invariants
- Mike Gordon's lecture notes on Hoare logic [1]