Erinevus lehekülje "Software Synthesis and Verification" redaktsioonide vahel
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P (Vain teisaldas lehekülje Formal Methods pealkirja Software Synthesis and Verification alla) |
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* Lab 5: UPPAAL | * Lab 5: UPPAAL | ||
** Assignment: Leader election protocol | ** Assignment: Leader election protocol | ||
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** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]] | ** Slides: [[Media:ITI0130_Lab3_IEEE1394.pdf|Explanation]] | ||
** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)] | ** [http://perso.ens-lyon.fr/pierre.lescanne/ENSEIGNEMENT/REECRITURE/ABRIAL/sldp.ieee1394.pdf The Leader Election Protocol (IEEE 1394)] | ||
** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394] | ** [http://link.springer.com/article/10.1023%2FA%3A1008764923992 Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394] | ||
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* Lab 6: UPPAAL | * Lab 6: UPPAAL | ||
** Homework defenses | ** Homework defenses | ||
Redaktsioon: 3. märts 2016, kell 07:35
Course code: ITI8531
Link: http://courses.cs.ttu.ee/pages/ITI0130
Lecturer: prof. Jüri Vain
Contact: juri.vain ätt ttu.ee, ICT-418
Previous courses: 2014
Time and place
Lectures: Thursdays 12:00, ICT-A1
Labs: Thursdays 10:00, ICT-405 - Evelin Halling (evelin.halling ätt ttu.ee)
News 2016
- Written exam I: at 14.00 on May 27, Room ICT-411
- Written exam II: at 14.00 on June 3, Room ICT-411
Lecture plan
- Lecture 1: Introduction
- Lecture 2: Modelling state transition systems
- Lecture 3: Temporal logic CTL*
- Lecture 4: CTL model checking
- Lecture 5: Timed automata and TCTL model checking
- Test 1: Model checking
- Lecture 7: Program specifications
- Lecture 8: Proving partial correctness of programs
- Lecture 9.1: Proof techniques (1): derived rules, backwards proof, annotations
- Lecture 9.2: Proof techniques (2): Array- and FOR-rule
- Lecture 10: Proving total correctness of while-programs
- Test 2: Deductive verification of sequential programs
- Lecture 11: Non-deterministic programs
- Lecture 12: Parallel programs with shared variables
- Lecture 13: Parallel programs with message passing
- Test 3: Deductive verification of non-deterministic and parallel programs
Labs
- Lab 1 -2: Introduction to modelling in UPPAAL
- UPPAAL website
- Small tutorial on UPPAAL
- Tutorial on UPPAAL
- Slides: UPPAAL introduction
- Model: Lamp example
- Query: Lamp example
- Lab 3: Introduction to modelling in UPPAAL
- Assignment: Coffee Machine
- Slides: Example and explanation
- Model: Coffee machine
- Query: Coffee machine
- Lab 4: UPPAAL
- Assignment: Reader-Writer (unreliable) communication protocol
- Slides: Example and explanation
- Lab 5: UPPAAL
- Assignment: Leader election protocol
- Slides: Explanation
- The Leader Election Protocol (IEEE 1394)
- Verification of a Leader Election Protocol: Formal Methods Applied to IEEE 1394
- Lab 6: UPPAAL
- Homework defenses
- Labs 7 - 16: Design-by-Contract (Cofoja), Key Tool
Exercises
- Exercises 1: Model checking (explicit and symbolic state)
- Exercises 2: Partial correctness of WHILE-programs
- Exercises 3: Partial correctness of non-deterministic and parallel programs